The present invention relates to a semiconductor integrated circuit, for instance a digital signal processor (referred to as xe2x80x9cDSPxe2x80x9d hereinafter), a microprocessor and so forth, more particularly, the invention relates to a semiconductor integrated circuit which can be used for the purpose of logical verification of the internal parts of the circuit and the data verification of the internal register.
Generally, the semiconductor integrated circuit includes a plurality of processing circuits for executing necessary processes. The term xe2x80x98processing circuitxe2x80x99 herein refers to a combination circuit which is constructed with logical circuits, for instance as an AND circuit, an OR circuit and so forth. The logic level of the output signal from such combination circuit is determined to be a predetermined logical level corresponding to the logical level of the input signal supplied thereto. However, should such combination circuit have a certain defect and/or should the change with the passage of time relating to its performance be not in an allowable range, the output signal comes to have a logical level which is neither the desired logical level nor responds to the logical level of the input signal. Thus, it is necessary to verify whether the semiconductor integrated circuit including such combination circuit normally operates or not, and execution of the logical verification increases its importance.
For the purpose of carrying out this logical verification, the semiconductor integrated circuit includes a plurality of scan-path registers. Each scan-path register is constituted with a data maintaining circuit which receives the input signal to the combination circuit or the output circuit therefrom. In case of ordinarily processing the signal which is externally inputted to the semiconductor integrated circuit (referred to as xe2x80x9cordinary processingxe2x80x9d hereinafter), the scan-path register operates to transfer its received input signal to the combination circuit or to output the signal outputted by the combination circuit to a certain circuit in the next stage. This circuit in the next stage indicates such a circuit that receives the output signal from the combination circuit and applies a desired processing thereto. In time of executing the logical verification over the combination circuit (referred to as xe2x80x9clogical verification timexe2x80x9d hereinafter), the scan-path registers are connected in sequence with each other, thereby constituting a shift register as a whole.
Regarding to the logical verification of the semiconductor integrate circuit using the scan-path registers, there has been published by Oki Denki Kogyo K.K. an article entitled xe2x80x9cScan-path Register.xe2x80x9d In the following, an example of a data system connection relating to the logical verification operation will be explained by way of the semiconductor integrated circuit using the scan-path register as disclosed in the above article, referring to FIG. 10 of the accompanying drawings.
Referring to FIG. 10, there is shown a diagram of a conventional semiconductor integrated circuit 800 which includes three combination circuits 811-1 through 811-3 to be logically verified. The semiconductor integrated circuit 800 also includes a plurality of signal terminals for exchanging the signal with external portions, to be more concrete, an input terminal MD for a mode setting signal, a first clock input terminal CL1, a second clock input terminal CL2, a data input terminal 880 for the Scan-path, and a data output terminal 881 for the Scan-path.
The input terminal MD for the mode setting signal receives the mode setting signal which is used for switching the operation of the scan-path register from the serial operation to the parallel operation or vice versa, both operations being described later. The first clock input terminal CL1 receives the first clock signal which is used under the first operating condition, that is, under the ordinary operating condition. The second clock input terminal CL2 receives the second clock signal under the second operating condition, namely in the logical verification time. The data input terminal 880 for the scan-path receives a data signal SIN which is used for the logical verification in the logical verification time. The data output terminal 881 for the scan-path outputs the data signal SOUT which is obtained as a result of the logical verification.
The semiconductor integrated circuit 800 further includes scan-path registers 810-1 through 810-n and 820-1 through 820-n (n: positive integer) as the data maintaining circuit, and a control signal generating circuit 840.
The scan-path registers 810-K (or 820-K) (K: positive integer but 1xe2x89xa6Kxe2x89xa6n) include a clock input terminal CK, a first data input terminal D, a second data input terminal SI, a first control signal input terminal K1, a second control signal input terminal K2, and an output terminal Q.
The control signal generating circuit 840 is connected with the mode setting signal input terminal MD, the first clock input terminal CL1, and the second clock input terminal CL2, respectively. This control signal generating circuit 840 generates a plurality of control signals C/!C, PC/!PC, and SC/!SC. The control signal C/!C represents either one or both of a control signal C and an inverted control signal !C having a logical level complementary to that of the control signal C.
The control signal C/!C is inputted to the clock input terminal CK of the scan-path register 810-K (or 820-K). The control signal PC/!PC is inputted to the first control signal input terminal K1 of the scan-path register 810-K (or 820-K). The control signal SC/!SC is inputted to the second control signal input terminal K2 of the scan-path register 810-K (or 820-K).
The output signal from the combination circuit 811-1 is inputted to the first data input terminal D of the scan-path register 810-K. The output signal from the combination circuit 811-2 is inputted to the first data input terminal D of the scan-path register 820-K. The second data input terminal SI of the scan-path register 810-K is connected with the output terminal Q of the scan-path register 810-(Kxe2x88x921). However, in case of K=1, the second data input terminal SI is connected to the data input terminal 880 for the scan-path.
The second data input terminal SI of the scan-path register 820-K is connected with the output terminal Q of the scan-path register 820-(Kxe2x88x921). However, in case of K=1, the second data input terminal SI is connected with the output terminal Q of the scan-path register 810-n. The output terminal Q of the scan-path register 810-K is also connected with the combination circuit 811-2 while the output terminal Q of the scan-path register 820-K is also connected with the combination circuit 811-3. In case of K=n, however, the output terminal Q is also connected with the output terminal 881 for the Scan-path.
It will now be explained in the following how to carry out the logical verification against the combination circuit by means of the scan-path register.
(1) Test Serial Input Operation
In this operation, the data SIN (referred to as xe2x80x9ctest vectorxe2x80x9d hereinafter) for logical verification is serially inputted to the data input terminal 880 for the Scan-path, thereby storing the data in all the scan-path registers 810-1 through 810-n and 820-1 through 820-n with the help of the shift operation. This operation is carried out in response the second clock signal CL2.
(2) Test Parallel Operation
In this operation, the test vector SIN stored in the scan-path registers, which are disposed on the input side of the combination circuit to be logically verified, is inputted to the above combination circuit, of which the output is then given to and stored in the scan-path registers which are disposed on the output side of the above combination circuit. This operation is performed in response to the second clock signal CL2. To be more concrete, referring to FIG. 10, assuming now that the combination circuit is the circuit 811-2, the scan-path registers on the input side are those which are denoted with reference numerals 810-1 through 810-n while the scan-path registers on the output side are those which are indicated with reference numerals 820-1 through 820-n. On the other hand, assuming that the combination circuit is the circuit 811-1, the scan-path registers on the input side are those which would be denoted with suitable reference numerals, not shown though, while the scan-path registers on the output side are those which are indicated with reference numerals 810-1 through 810-n. Similarly, assuming that the combination circuit is the circuit 811-3, the scan-path registers on the input side are those which are indicated with reference numerals 820-1 through 820-n while the scan-path registers on the output side are those which to be are indicated with suitable reference numerals not shown, too.
(3) Test Serial Output Operation
In this operation, the resultant output SOUT of the combination circuit, which is stored in the scan-path registers on the output side of the combination circuit, is serially outputted from the data output terminal 881 for the scan-path with the help of the shift operation. This operation is executed in response to the second clock signal CL2.
(4) Comparison Operation Using Expected Value
In this operation, there is made a comparison between an expected value and the data outputted from the data output terminal 881 for the Scan-path. In this case, the expected value is defined as a data that has to be outputted from a combination circuit when it normally operates. For instance, the expected value is the data that has to be outputted from the normally operating combination circuit 811-2 when the test vector SIN stored in the scan-path registers 810-1 through 810-n is inputted to the combination circuit 811-2. That is, if the output data SOUT outputted from the data output terminal 881 for the scan-path coincides with the expected value, it can be determined that the combination circuit 811-2 is normal. Contrary to this, if the output data SOUT outputted from the data output terminal 881 for the scan-path does not coincide with the expected value, it can be determined that the combination circuit 811-2 is not normal.
However, in case of executing the logical verification of the semiconductor integrated circuit by means of the scan-path register as described above, all or the greater part of the registers in the semiconductor integrated circuit have to be replaced by the scan-path registers, and also, these scan-path registers have to be connected with each other in a shift register fashion. Needless to say, this results in the unnecessary enlargement in the scale of the semiconductor integrated circuit. Thus, this becomes a problem to be solved.
Further, in the semiconductor integrated circuit, a plurality of registers are often put together in a group, which is handled as a register group. In this case, in order to make the scale of the semiconductor integrated circuit as smaller as possible, there is a tendency for the register group to be constituted so as to have a structure similar to that of the memory. Therefore, each register forming the register group can not be connected with each other in a shift register fashion. As a result, it becomes possible neither to execute the test serial input operation nor to carry out the test serial output operation, as far as both require the shift operation. Thus, this presents another problem to be solved.
Still further, in the prior art method, in order to execute the shift operation, a large number of registers have to be connected in a shift register fashion such that the timing lag of the clock signal (referred to as xe2x80x9cclock skewxe2x80x9d hereinafter) in each register is exactly matched with each other. For this, the addition of a delay element such as a buffer has to be considered for matching the clock skews with each other when designing the circuit and the pattern. This addition of the delay element naturally results not only in the undesirable enlargement in the scale of the semiconductor integrated circuit but also in the increase of power consumption thereof. Thus, this causes still another problem to be solved.
Accordingly, the invention has been made in view of the problems as described above, and one object of the invention is to provide a novel and improved semiconductor integrated circuit which can possibly minimize the scale of the circuit.
Further, the other object of the invention is to provide a novel and improved semiconductor integrated circuit, of which the power consumption can be reduced as smaller as possible.
In order to solving the problems as described, according to the invention, there is provided a semiconductor integrated circuit having the function of logically verifying the internal circuit thereof, which includes a plurality of units to be logically verified, of which each independently operates in the ordinary operation and includes data maintain circuits which are operable as a shift register when connected in sequence with each other in the logical verification operation; an input portion to which the instruction of logical verification is externally inputted; an instruction register portion in which the instruction of logical verification is stored; an instruction decoder circuit which decodes the instruction stored in the instruction register portion and executes the instruction of the logical verification against the units; and an output portion for externally outputting the processing result of the units.
According to the semiconductor integrated circuit as constituted above, the instruction of the logical verification can be directly inputted to the instruction register through the external terminal i.e. the above input portion, and further each unit is provided with a scan-path register i.e. a data maintain circuit, so that the scale of the semiconductor integrated circuit can be reduced to a great extent and the logical verification can be executed thereby.
Further, in the semiconductor integrated circuit as constituted above, the above output portion may include a data bus which is commonly connected with the plurality of units, respectively, and a common register portion which stores the data outputted to the data bus from the plurality of units.
Accordingly, as mentioned above, the above output portion may include the common data bus connecting with each of the plurality of units and one common register connected with the data bus, and further the instruction of the logical verification can be directly inputted to the instruction register through the external terminal i.e. the above input portion, so that the scale of the semiconductor integrated circuit can be reduced to a great extent and the logical verification can be executed thereby.
Still further, the above output portion may include a parallel output portion which outputs in parallel the data stored in the common register portion. With this, the data stored in the common register portion can be directly observed through the common register output terminal, thereby the logical verification time being considerably shortened.
Still further, the above input portion may include a parallel input portion which inputs in parallel the instruction of the logical verification to the instruction register portion. Accordingly, the instruction to be stored in the instruction register can be inputted in parallel thereto through the instruction register input terminal. With this, the logical verification time can be fairly shortened.
Still further, the above input portion may include a common register input terminal for inputting the data to the common register portion, and the above output portion may include an instruction register output terminal for outputting the instruction of the instruction register portion.
Accordingly, in the above semiconductor integrated circuit, it is made possible to directly input the instruction to the instruction register portion through the external terminal and the common data bus is connected with the common register portion. Therefore, if there are additionally provided, without changing the basic constitution of the semiconductor integrated circuit, a common register scan input terminal, a common register scan output terminal, an instruction register scan input terminal, and an instruction register scan output terminal, it becomes possible for the semiconductor integrated circuit to have the function of emulation which enables the observation of the internal register or the setting of the data to the internal register, during the operation of the semiconductor integrated circuit. Still further, the common register portion can be used as an general auxiliary register in the ordinary operation, so that it can be effectively used in the ordinary operation and in the emulating operation as well.
Preferably, the common register portion includes a common register which is used in the ordinary operation and a common back register which is used in the emulating operation. With this, the common register can be used exclusively in the ordinary operation while the common back register can be exclusively used in the emulating operation. This can also shorten the time needed for emulation.
Preferably, the instruction register portion may include an instruction register which is used in the ordinary operation and an instruction back register which is used in the emulating operation. With this, the instruction register can be used exclusively in the ordinary operation while the instruction back register can be exclusively used in the emulating operation. This can also shorten the time needed for emulation. Further, even in case of processing the data of the internal register which might be changed or destroyed through the emulating operation, the time of the emulating operation can be shortened by adopting the same construction as the above.